Z85C3008PEG Datasheet, PDF (44/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
36
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 12
D7 D6 D5 D4 D3 D2 D1 D0
0 0 No Reset
0 1 Channel Reset B
1 0 Channel Reset A
1 1 Force Hardware Reset
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
0 0 NRZ
0 1 NRZI
1 0 FM1 (Transition = 1)
1 1 FM1 (Transition = 0)
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
VIS
NV
DLC
MIE
Status High/Status Low
Software INTACK Enable
6-Bit/8-Bit Sync
Loop Mode
Abort/Flag on Underrun
Mark/Flag Idle
Go Active on Poll
CRC Preset I/O
0 0 TRxC Out = Xtal Output
0 1 TRxC Out = Transmit Clock
1 0 _{TRxC Out = BR Generator Output}
1 1 _{TRxC Out = DPLL Output}
TRxC O/I
0 0 Transmit Clock = RTxC Pin
0 1 Transmit Clock = TRxC Pin
1 0 Transmit Clock = BR Generator Output
1 1 Transmit Clock = DPLL Output
0 0 Receive Clock = RTxC Pin
0 1 Receive Clock = TRxC Pin
1 0 Receive Clock = BR Generator Output
1 1 Receive Clock = DPLL Output
RTxC Xtal/No Xtal
Write Register 13
D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Lower Byte of
Time Constant
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
Upper Byte of
Time Constant
BR Generator Enable
BR Generator Source
DTR/Request Function
Auto Echo
Local Loopback
0 0 0 Null Command
0 0 1 Enter Search Mode
0 1 0 Reset Missing Clock
0 1 1 Disable DPLL
1 0 0 Set Source = BR Generator
1 0 1 Set Source = RTxC
1 1 0 Set FM Mode
1 1 1 Set NRZI Mode
Write Register 15
D7 D6 D5 D4 D3 D2 D1 D0
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
Figure 18. Write Register Bit Functions
PS011706-0511
Functional Descriptions