Z85C3008PEG Datasheet, PDF (58/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
50
WR
48
47
48
RD
Figure 32. Z85C30 Reset Timing Diagram
Table 6 lists the Read/Write timing parameters for the Z85C30 device.
Table 6. Z85C30 Read/Write Timing
8.5 MHz
10 MHz
16 MHz
No Symbol
1 TwPCI
2 TwPCh
Parameter
PCLK Low Width
PCLK High Width
Min
Max
Min
Max
Min
Max
45
2000
40
2000
26
2000
45
2000
40
2000
26
2000
3 TfPC
PCLK Fall Time
10
10
5
4 TrPC
PCLK Rise Time
10
10
5
5 TcPC
PCLK Cycle Time
118 4000 100 4000
61
4000
6 TsA(WR)
Address to WR Fall
66
50
35
Setup Time
7 ThA(WR)
Address to WR Rise
0
0
0
Hold Time
8 TsA(RD)
Address to RD Fall
66
50
35
Setup Time
9 ThA(RD)
Address to RD Rise
0
0
0
Hold Time
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchro-
nized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011706-0511
Electrical Characteristics