Z85C3008PEG Datasheet, PDF (26/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
18
Register
WR13
WR14
WR15
Table 2. SCC Write Register Functions (continued)
Function
Upper byte of Baud Rate Generator time constant
Miscellaneous control bits
External/Status interrupt control
The following three methods move data, status and control information in and out of the
SCC; each is described in this section.
• Polling
• Interrupts (vectored and nonvectored)
• CPU/DMA Block Transfer, in which BLOCK TRANSFER mode can be implemented
under CPU or DMA control
Polling
When polling, all interrupts are disabled. Three status registers in the SCC are automati-
cally updated when any function is performed. For example, End-Of-Frame in SDLC
mode sets a bit in one of these status registers. The purpose of polling is for the CPU to
periodically read a status register until the register contents indicate the need for data to be
transferred. Only one register is read, and depending on its contents, the CPU either writes
data, reads data, or continues. Two bits in the register indicate the need for data transfer.
An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both channels resides in one register.
Interrupts
The SCC’s interrupt structure supports vectored and nested interrupts. Nested interrupts
are supported with the interrupt acknowledge feature (INTACK pin) of the SCC.
This allows the CPU to recognize the occurrence of an interrupt, and reenable higher pri-
ority interrupts. Because an INTACK cycle releases the INT pin from the active state, a
higher priority SCC interrupt or another higher priority device can interrupt the CPU.
When an SCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an
interrupt vector can be placed on the data bus. This vector is written in WR2 and can be
read in RR2A or RR2B. To speed interrupt response time, the SCC can modify three bits
in this vector to indicate status. If the vector is read in Channel A, status is never included.
If the vector is read in Channel B, status is always included.
Each of the six sources of interrupts in the SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits associated with the interrupt source.
PS011706-0511
Functional Descriptions