Z85C3008PEG Datasheet, PDF (61/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
53
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
10 MHz
16 MHz
No Symbol
Parameter
Min
Max
Min
Max
Min
Max
35b TdWRr(REQ)³ WR Fall to DTR/REQ
168
100
70
Not Valid
36 TdRDrrREQ) RD Rise to DTR/REQ
NA
NA
NA
Not Valid Delay
37 TdPC(INT) PCLK Fall to INT Valid
500
320
175
Delay
38 TdIAi(RD)⁴ INTACK to RD Fall
145
90
50
(Ack) Delay
39 TwRDA
RD (Acknowledge)
145
125
75
Width
40 TdRDA(DR) RD Fall (Ack) to Read 135
120
70
Data Valid Delay
41 TsiEI(RDA) IEI to RD Fall (Ack)
95
80
50
Setup Time
42 ThIEI(RDA) IEI to RD Rise (Ack)
0
0
0
Hold Time
43 TdIElrIEO) IEI to IEO Delay Time
95
80
45
44 TdPC(IEO)
PCLK Rise to IEO
Delay
195
175
80
45 TdRDA(INT)² RD Fall to INT Inactive
480
320
200
Delay
46 TdRDrWRQ) RD Rise to WR Fall
15
15
10
Delay for No Reset
47 TdWRQ(RD) WR Rise to RD Fall
15
15
10
Delay for No Reset
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchro-
nized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011706-0511
Electrical Characteristics