Z85C3008PEG Datasheet, PDF (67/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
59
Table 8 lists the system timing characteristics for the Z85C30 device.
Table 8. Z85C30 System Timing Table
8.5 MHz
No Symbol
Parameter
Min
1 TdRXC(REQ)
RxC High to W/REQ Valid^1,2
8
2 TdRXC(W)
RxC High to Wait Inactive^1,2,3
8
3 TdRdXC(SY)
RxC High to SYNC Valid^1,2
4
4 TsRXC(INT)
RxC High to INT Valid^1,2,3
10
5 TdTXC(REQ)
TxC Low to W/REQ Valid^2,4
5
6 TdTXC(W)
TxC Low to Wait Inactive^2,3,4
5
7 TdTXC(DRQ)
TxC Low to DTR/REQ Valid^3,4
4
8 TdTXC(INT)
TxC Low to INT Valid^2,3,4
6
9a TdSY(INT)
SYNC to INT Valid ^2,3
2
9b TdSY(INT)
SYNC to INT Valid^2,3,5
2
10 TdEXT(INT)
DCD or CTS to INT Valid^2,3
2
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. Units equal to TcPc.
3. Open-drain output, measured with open-drain test load.
4. TxC is TRxC or RTxC whichever is supplying the transmit clock.
5. Units equal to AS.
Max
12
14
7
16
8
11
7
10
6
3
6
10 MHz
Min Max
8 12
8 14
4
7
10 16
5
8
5 11
4
7
6 10
2
6
2
3
2
6
16 MHz
Min Max
8 12
8 14
4 70
10 16
5
8
5 11
4
7
6 10
2
6
2
3
2
6
Table 9 provides the Read/Write timing characteristics for the Z85C30 device.
Table 9. Z85C30 Read/Write Timing
No Symbol
1 TwPCI
2 TwPCh
3 TfPC
4 TrPC
5 TcPC
6 TsA(WR)
7 ThA(WR)
8 TsA(RD)
Parameter
PCLK Low Width
PCLK High Width
PCLK Fail Time
PCLK Rise Time
PCLK Cycle Time
Address to WR Fail Setup Time
Address to WR Rise Hold Time
Address to RD Fall Setup Time
8.5 MHz
Min Max
45 2000
45 2000
10
10
118 4000
66
0
66
10 MHz
Min Max
40 2000
40 2000
10
10
100 4000
50
0
50
16 MHz
Min Max
26 2000
26 2000
5
5
61 4000
35
0
35
PS011706-0511
Electrical Characteristics