Z85C3008PEG Datasheet, PDF (72/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
64
Table 10. Z80C30 Read/Write Timing¹ (continued)
8 MHz
10 MHz
No Symbol
23 TdDS(DRz)
24 TdA(DR)
25 TdDS(W)
26 TdDSf(REQ)
27 TdDSr(REQ)
28 TdAS(INT)
29 TdAS(DSA)
30 TwDSA
31 TdDSA(DR)
32 TsiEI(DSA)
33 ThIEI(DSA)
34 TdIEI(IEO)
35 TdAS(IEO)
36 TdDSA(INT)
37 TdDS(ASQ)
Parameter
DS Rise to Read Data Float Delay⁴
Min Max Min Max
40
35
Address Required Valid to Read Data
260
210
Valid Delay
DS Fall to Wait Valid Delay⁵
170
160
DS Fall to W/REQ Not Valid Delay
170
160
DS Fall to DTR/REQ Not Valid Delay
AS Rise to INT Valid Delay⁵
4TcPC
500
4TcPC
500
AS Rise to DS Fall (Acknowledge)
250
225
Delay⁶
DS (Acknowledge) Low Width
150
125
DS Fall (Acknowledge) to Read Data
140
120
Valid Delay
IEI to DS Fall (Acknowledge) Setup
80
80
Time
IEI to DS Rise (Acknowledge) Hold
0
0
Time
IEI to IEO Delay
AS Rise to IEO Delay^g
90
90
200
175
DS Fall (Acknowledge) to INT Inactive
450
450
Delay⁵
DS Rise to AS Fall Delay for No Reset 15
15
38 TdASQ(DS)
AS Rise to DS Fall Delay for No Reset 20
15
39 TwRES
AS and DS Coincident Low for Reset^h 150
100
40 TwPCI
PCLK Low Width
50
1000
40
1000
Notes:
1. Units in nanoseconds (ns) unless otherwise noted.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Parameter applies only between transactions involving the SCC.
4. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a min-
imum AC load.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each
device separating them in the daisy chain.
7. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
8. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing ref-
erences assume 20 V for a logic “1” and 08 V for a logic “0”.
PS011706-0511
Electrical Characteristics