Z85C3008PEG Datasheet, PDF (37/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
29
DMA the ability to continue to transfer data into memory so that the CPU can examine the
message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.
The byte count and status bits are accessed through Read Registers 6 and 7. Read Regis-
ters 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status FIFO
is separate from the 3-byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the
DMA controller to transfer the next frame into memory while the CPU verifies that the
message was properly received.
Summarizing the operation; data is received, assembled, and loaded into the eight byte
FIFO before being transferred to memory by the DMA controller. When a flag is received
at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status
bits are loaded into the status FIFO for verification by the CPU. The CRC checker auto-
matically resets in preparation for the next frame which can begin immediately. Because
the byte count and status are saved for each frame, the message integrity is verified at a
later time. The status information for up to 10 frames is stored before a status FIFO over-
run occurs.
If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and
the counter resets for the next frame.
FIFO Detail
For more details about FIFO operation, see Figure 13 on page 30.
Enable/Disable
This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the
SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and go
directly to the bus interface (the FIFO pointer logic is reset either when disabled or
through a channel or Power-On Reset). When the FIFO mode is disabled, the SCC is
downward-compatible with the NMOS Z8530. The FIFO mode is disabled on power-up
(WR15 D2 is set to 0 on reset). The effects of backward compatibility on the register set
are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and
RR7 is an image of RR3. For more details about the added registers, see Figure 16 on page
34. The status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO
is enabled, the bit is set to 1; otherwise, it resets.
Read Operation
When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or
registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location
of the FIFO to become empty. Status is read after reading the byte count, otherwise the
count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer
is switched allowing status to read directly from the status register. Reads from RR7 and
PS011706-0511
Functional Descriptions