Z85C3008PEG Datasheet, PDF (24/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
16
Internal Data Bus
CPU/I/O
I/O Data buffer
Upper Byte (WR13) Lower Byte (WR12)
Time Constant
Time Constant
Status FIFO
10 X 19 Frame
Rec. Error FIFO
3 Byte Deep
Rec. Error FIFO
3 Byte Deep
BRG
Input
16-Bit Down Counter
DIV 2
BRG
Output
14-Bit Counter
Hunt Mode (BISYNC)
Rec. Error Logic
DPLL
IN
DPLL
DPLL
OUT
Internal TXD
SYNC Register
& Zero Delete
3-Bit
Receive Shift
Register
RXD
1-Bit
MUX
NRZI Decode
MUX
To Transmit Section
SDLC-CRC
CRC Delay
Register (8 bits)
CRC
Checker
SYNC
CRC
CRC Result
Figure 7. SCC Receive Data Path
I/O Interface Capabilities
System communication to and from the SCC device is performed through the SCC’s regis-
ter set. There are sixteen Write registers and eight Read registers.
Throughout this document, Write and Read registers are referenced with the following
notation:
• ‘WR’ for Write Register
• ‘RR’ for Read Register
PS011706-0511
Functional Descriptions