Z85C3008PEG Datasheet, PDF (59/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
51
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
10 MHz
16 MHz
No Symbol
Parameter
Min
Max
Min
Max
Min
Max
10 TsiA(PC)
INTACK to PCLK Rise 20
20
15
Setup Time
11 TsiAi(WR)¹ INTACK to WR Fall
140
120
70
Setup Time
12 ThIA(WR)
INTACK to WR Rise
0
0
0
Hold Time
13 TsiAi(RD)¹
INTACK to RD Fall
140
120
70
Setup Time
14 ThIA(RD)
INTACK to RD Rise
0
0
0
Hold Time
15 ThIA(PC)
INTACK to PCLK Rise 38
30
15
Hold Time
16 TsCEI(WR) CE Low to WR Fall
0
0
0
Setup Time
17 ThCE(WR) CE to WR Rise Hold
0
0
0
Time
18 TsCEh(WR) CE High to WR Fall
58
Setup Time
19 TsCEI(RD)¹ CE Low to RD Fall
0
Setup Time
20 ThCE(RD)¹ CE to RD Rise Hold
0
Time
21 TsCEh(RD)¹ CE High to RD Fall
58
Setup Time
22 TwRDI¹
RD Low Width
145
50
30
0
0
0
0
50
30
125
70
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchro-
nized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011706-0511
Electrical Characteristics