Z85C3008PEG Datasheet, PDF (48/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
40
Write Cycle Timing
Figure 22 displays Write cycle timing. Addresses on A/B and D/C and the status on
INTACK must remain stable throughout the cycle. If CE falls after WR falls, or if CE rises
before WR rises, the effective WR is shortened. Data must be valid before the rising edge
of WR.
A/B, D/C
INTACK
CE
WR
A AAddd Address Valid
D7-D0
Data Valid
Figure 22. Write Cycle Timing
Interrupt Acknowledge Cycle Timing
Figure 23 displays an Interrupt Acknowledge cycle timing. Between the time INTACK
goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle.
If there is an interrupt pending in the SCC and IEI is High when RD falls, the Acknowl-
edge cycle is intended for the SCC. In this case, the SCC can be programmed to respond to
RD Low by placing its interrupt vector on D7-D0. It then sets the appropriate Interrupt-
Under-Service latch internally.
If the external daisy chain is not used, AC parameter #38 is required to settle the interrupt
priority daisy chain internal to the SCC. If the external daisy chain is used, you must fol-
low the equation in Table 6 on page 50 for calculating the required daisy-chain settle time.
PS011706-0511
Functional Descriptions