Z85C3008PEG Datasheet, PDF (33/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
25
Controller
Secondary #1
Secondary #4
Secondary #2
Secondary #3
Figure 11. An SDLC Loop
A secondary station in an SDLC Loop is always listening to the messages sent around the
loop and passes these messages to the rest of the loop by retransmitting them with a one-
bit-time delay. The secondary station places its own message on the loop only at specific
times.
The controller signals that secondary stations can transmit messages by sending a special
character, called an End Of Poll (EOP), around the loop. The EOP character is the bit pat-
tern 11111110. Because of zero insertion during messages, this bit pattern is unique and
easily recognized.
When a secondary station contains a message to transmit and recognizes an EOP on the
line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the
effect of turning the EOP into a flag sequence. The secondary station now places its mes-
sage on the loop and terminates the message with an EOP. Any secondary stations further
down the loop with messages to transmit append their messages to the message of the first
secondary station by the same process. Any secondary stations without messages to send
echo the incoming message and are prohibited from placing messages on the loop (except
when recognizing an EOP). In SDLC Loop mode, NRZ, NRZI, and FM coding can be
used.
The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10-
deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the
DMA the ability to continue to transfer data into memory so that the CPU can examine the
PS011706-0511
Functional Descriptions