Z85C3008PEG Datasheet, PDF (49/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
41
INTACK
RD
D7–D0
Vector
Figure 23. Interrupt Acknowledge Cycle Timing
Z80C30 Timing
The SCC generates internal control signals from AS and DS that are related to PCLK.
Because PCLK has no phase relationship with AS and DS, the circuitry generating these
internal control signals must provide time for metastable conditions to disappear. This
gives rise to a recovery time related to PCLK. The recovery time applies only between bus
transactions involving the SCC. The recovery time required for proper operation is speci-
fied from the falling edge of DS in the first transaction involving the SCC to the falling
edge of DS in the second transaction involving the SCC. The timings for Z80C30 device is
described below:
• Read Cycle Timing
• Write Cycle Timing
• Interrupt Acknowledge Cycle Timing
Read Cycle Timing
Figure 24 displays the Read cycle timing. The address on AD7–AD0 and the state of CS0
and INTACK are latched by the rising edge of AS. R/W must be High to indicate a Read
cycle. CS1 must also be High for the Read cycle to occur. The data bus drivers in the SCC
are then enabled while DS is Low.
PS011706-0511
Functional Descriptions