Z85C3008PEG Datasheet, PDF (60/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
52
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
10 MHz
16 MHz
No Symbol
Parameter
Min
Max
Min
Max
Min
Max
23 TdRD(DRA) RD Fall to Read Data
0
0
0
Active Delay
24 TdRDr(DR) RD Rise to Data Not
0
0
0
Valid Delay
25 TdRDI(DR) RD Fall to Read Data
135
120
70
Valid Delay
26 TdRD(DRz) RD Rise to Read Data
38
35
30
Float Delay
27 TdA(DR)
Addr to Read Data
Valid Delay
210
160
100
28 TwWRI
WR Low Width
145
125
75
29 TdWR(DW) WR Fall to Write Data
35
35
20
Valid Delay
30 ThDW(WR) Write Data to WR Rise 0
0
0
Hold Time
31 TdWR(W)² WR Fall to Wait Valid
168
100
50
Delay
32 TdRD(W)²
RD Fall to Wait Valid
168
100
50
Delay
33 TdWRf(REQ) WR Fall to W/REQ Not
168
120
70
Valid Delay
34 TdRDf(REQ)³ RD Fall to W/REQ Not
168
120
70
Valid Delay
35a TdWRr(REQ) WR Fall to DTR/REQ
Not Valid
4TcPc
4TcPc
4TcPc
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchro-
nized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011706-0511
Electrical Characteristics