Z85C3008PEG Datasheet, PDF (62/81 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
54
Table 6. Z85C30 Read/Write Timing (continued)
8.5 MHz
10 MHz
16 MHz
No Symbol
48 TwRES
49a Trc^e
49b Trci^f
Parameter
Min
Max
Min
Max
Min
Max
WR and RD Low for
145
100
75
Reset
Valid Access Recovery 3.5TcPc 3.5TcPc 3.5TcPc
Time
RD or WR Fall to PC
0
0
0
Fall Setup Time
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Open-drain output, measured with open-drain test load.
3. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).
4. Parameter is system-dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of
TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each
device separating them in the daisy chain.
5. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchro-
nized to PCLK falling edge, then TrC = 3TcPc.
6. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
PS011706-0511
Electrical Characteristics