Z86D73 Datasheet, PDF (71/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
65
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 18.
Table 18. WDT Time Select*
D1
D0
Timeout of Internal RC OSC
0
0
5 ms min
0
1
10 ms min
1
0
20 ms min
1
1
80 ms min
Note:
*TpC = XTAL clock cycle. The default on reset is 10 ms.
Timeout of XTAL Clock
256 TpC
512 Tpc
1024 TpC
4096 TpC
WDTMR During HALT (D2)
This bit determines whether or not the WDT is active during HALT Mode. A 1 indi-
cates active during HALT. The default is 1. See Figure 39.
PS019402-1103
PRELIMINARY