Z86D73 Datasheet, PDF (61/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
55
Table 15. Interrupt Types, Sources, and Vectors
Name
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Source Vector Location Comments
P32
0,1
External (P32), Rising Falling Edge Triggered
P33
2,3
P31, T_IN 4,5
T16
6,7
External (P33), Falling Edge Triggered
External (P31), Rising Falling Edge Triggered
Internal
T8
8,9
LVD
10,11
Internal
Internal
When more than one interrupt is pending, priorities are resolved by a programma-
ble priority encoder controlled by the Interrupt Priority Register. An interrupt
machine cycle is activated when an interrupt request is granted. As a result, all
subsequent interrupts are disabled, and the Program Counter and Status Flags
are saved. The cycle then branches to the program memory vector location
reserved for that interrupt. All Z86D73 interrupts are vectored through locations in
the program memory. This memory location and the next byte contain the 16-bit
address of the interrupt service routine for that particular interrupt request. To
accommodate polled interrupt systems, interrupt inputs are masked, and the Inter-
rupt Request register is polled to determine which of the interrupt requests require
service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. These interrupts are programmable by the user. The software can poll
to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in Table 16.
Table 16. IRQ Register*
IRQ
Interrupt Edge
D7
D6
IRQ2 (P31) IRQ0 (P32)
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Notes: F = Falling Edge; R = Rising Edge
*In stop mode, the comparators are turned off.
PS019402-1103
PRELIMINARY