Z86D73 Datasheet, PDF (39/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
33
Register Description
LVD(D)0Ch Low-Voltage Detection Register
Note: The LVD flag will be valid after enabling the detection for 20 µS (design
estimation, not tested in production). LVD does not work at STOP mode. It
must be disabled during STOP mode in order to reduce current.
Field
LVD
Bit Position
765432--
------1-
-------0
*Default after POR
R1
0*
R/W 1
0*
Description
Reserved
No Effect
LV flag set
LV flag reset
Enable LVD
Disable LVD
Note: Do not modify register P01M while checking a low-voltage condition.
Switching noise of both ports 0 and 1 together might trigger the LVD flag.
HI8(D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register is used to hold the number of counts when the input signal
is 1.
Field
Bit Position
T8_Capture_HI 76543210
Description
R Captured Data
W No Effect
L08(D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register is used to hold the number of counts when the input signal
is 0.
Field
Bit Position
T8_Capture_L0 76543210
Description
R Captured Data
W No Effect
PS019402-1103
PRELIMINARY