Z86D73 Datasheet, PDF (42/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
36
Single/Modulo-N
When set to 0 (modulo-n), the counter reloads the initial value when the terminal
count is reached. When set to 1 (single pass), the counter stops when the terminal
count is reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, a 1
should be written to its location.
Caution: Writing a 1 is the only way to reset the Terminal Count status condition.
Therefore, reset this bit before using/enabling the counter/timers.
The first clock of T8 might not have complete clock width and can
occur any time when enabled.
Note: Care must be taken when using the OR or AND commands to manipulate
CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These
instructions use a Read-Modify-Write sequence in which the current status
from the CTR0 and CTR1 registers is ORed or ANDed with the designated
value and then written back into the registers.
Example
When the status of bit 5 is 1, a timer reset condition occurs.
T8 Clock
This bit defines the frequency of the input signal to T8.
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon
a positive or negative edge detection in demodulation mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
PS019402-1103
PRELIMINARY