Z86D73 Datasheet, PDF (25/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
19
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC net-
work to the on-chip oscillator input. Additionally, an optional external single-phase
clock can be coded to the on-chip oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC net-
work to the on-chip oscillator output.
R/W Read/Write (Output, Write Low)
The R/W signal is Low when the CCP is writing to the external program or data
memory.
R/RL (Input)
This pin, when connected to GND, disables the internal ROM and forces the
device to function as a ROMless Z8.
Note: When left unconnected or pulled high to V_CC, the part functions
normally as a Z8 ROM version.
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port or as an address port for
interfacing external memory. The output drivers are push-pull or open-drain con-
trolled by bit D2 in the PCON register.
For external memory references, Port 0 can provide address bits A11–A8 (lower
nibble) or A15–A8 (lower and upper nibble), depending on the required address
space. If the address range requires 12 bits or less, the upper nibble of Port 0 can
be programmed independently as I/O while the lower nibble is used for address-
ing. If one or both nibbles are needed for I/O operation, they must be configured
by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured
as an input port.
Port 0 is set in the high-impedance mode (if selected as an address output), along
with Port 1 and the control signals AS, DS, and R/W through P3M bits D4 and D3
(see Figure 10).
A ROM mask option is available to program 0.4 V_DD CMOS trip inputs on P00–
P03. This option allows direct interface to mouse/trackball IR sensors.
PS019402-1103
PRELIMINARY