Z86D73 Datasheet, PDF (27/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
21
Port 1 (P17–P10)
Port 1 (see Figure 11) is a multiplexed Address (A7–A0) and Data (D7–D0),
CMOS-compatible port. Port 1 is dedicated to the ZiLOG ZBus^®-compatible mem-
ory interface. The operations of Port 1 are supported by the Address Strobe (AS)
and Data Strobe (DS) lines and by the Read/Write (R/W) and Data Memory (DM)
control lines. Data memory read/write operations are done through this port. If
more than 256 external locations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and
R/W, allowing the Z86D73 to share common resources in multiprocessor and
DMA applications. Port 1 can also be configured for standard port output mode.
After POR, Port 1 is configured as an input port. The output drivers are either
push-pull or open-drain and are controlled by bit D1 in the PCON register.
Z86D73
OTP
8
Port 1 (I/O or AD7–AD0)
Open-Drain
OEN
Out
In
Figure 11. Port 1 Configuration
Mask ^VCC
Option
Resistive
transistor
pull-up
Pad
PS019402-1103
PRELIMINARY