Z86D73 Datasheet, PDF (46/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
40
Table 13. CTR2 (D)02h: Counter/Timer16 Control Register (Continued)
Field
T16 _Clock
Bit Position
---43---
R/W
Capture_INT_Mask
-----2--
R/W
Counter_INT_Mask
------1-
R/W
P35_Out
-------0
R/W
Note:
*Indicates the value upon Power-On Reset.
Value
00
01
10
11
0
1
0
0*
1
Description
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture
Int.
Enable Data Capture
Int.
Disable Timeout Int.
Enable Timeout Int.
P35 as Port Output
T16 Output on P35
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In Transmit Mode, when set to 0, the counter reloads the initial value when the ter-
minal count is reached. When set to 1, the counter stops when the terminal count
is reached.
In Demodulation Mode, when set to 0, T16 captures and reloads on detection of
all the edges. When set to 1, T16 captures and detects on the first edge but
ignores the subsequent edges. For details, see the description of T16 Demodula-
tion Mode on page 50.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write
a 1 to this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
PS019402-1103
PRELIMINARY