Z86D73 Datasheet, PDF (24/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
18
Table 8. Additional Timing (Continued)
T_A = 0 °C to +70 °C
8.0 MHz
No Sym
12 Twdt
Parameter
V_CC
Min
Watch-Dog Timer 2.0 V
12
Max
Delay Time
3.6 V
5
2.0 V
25
3.6 V
10
2.0 V
50
3.6 V
20
2.0 V
200
3.6 V
80
Notes:
1. Timing Reference uses 0.9 V_CC for a logic 1 and 0.1 V_CC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0.
5. For internal RC oscillator.
Stop-Mode
Recovery
Units Notes (D1, D0)
ms 5
0, 0
ms 5
ms 5
0, 1
ms 5
ms 5
1, 0
ms 5
ms 5
1, 1
ms 5
Pin Functions
DS (Output, Active Low)
The Data Strobe is activated one time for each external memory transfer. For a
READ operation, data must be available prior to the trailing edge of DS. For
WRITE operations, the falling edge of DS indicates that output data is valid.
AS (Output, Active Low)
Address Strobe is pulsed one time at the beginning of each machine cycle.
Address output is through Port 0/Port 1 for all external programs. Memory address
transfers are valid at the trailing edge of AS. Under program control, AS is placed
in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/
Write.
PS019402-1103
PRELIMINARY