Z86D73 Datasheet, PDF (66/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
60
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 35). The
purpose of this control is to selectively reduce device power consumption during
normal processor execution (SCLK control) and/or HALT Mode (where TCLK
sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0.
OSC
÷2
÷ 16
SMR, D0
SCLK
TCLK
Figure 35. SCLK Circuit
Stop-Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the STOP recovery
(Figure 36 and Table 17).
PS019402-1103
PRELIMINARY