Z86D73 Datasheet, PDF (65/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
59
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop-
Mode Recovery (Figure 34). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input is required from the recovery source. Bit 5 controls the reset delay
after recovery. Bits D2, D3, and D4 or the SMR register specify the source of the
Stop-Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16
or not. The SMR is located in Bank F of the Expanded Register Group at address
0Bh.
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default setting after reset
* * Default setting after reset and stop-mode recovery
* * * At the XOR gate input
Figure 34. Stop-Mode Recovery Register
PS019402-1103
PRELIMINARY