Z86D73 Datasheet, PDF (37/92 Pages) Zilog, Inc. – 40/44/48-Pin Low-Voltage IR OTP

Z86D73
40/44/48-Pin Low-Voltage IR OTP
31
LD RP, #0Dh
LD RP, #7Dh
LD 71h, 2
LD R1, 2
; Select ERF D for access to bank D
; (working register group 0)
; Select expanded register bank D and working
; register group 7 of bank 0 for access.
; CTRL2→register 71h
; CTRL2→register 71h
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose reg-
isters, 16 control and status registers (R0–R3, R4–R239, and R240–R255,
respectively), and two expanded registers groups in Banks D (see Table 10) and
F. Instructions can access registers directly or indirectly through an 8-bit address
field, thereby allowing a short, 4-bit register address to use the Register Pointer
(Figure 18). In the 4-bit mode, the register file is divided into 16 working register
groups, each occupying 16 continuous locations. The Register Pointer addresses
the starting location of the active working register group.
Note: Working register group E0–EF can only be accessed through
working registers and indirect addressing modes.
r₇ r₆ r₅ r₄ r₃ r₂ r₁ r₀ R253
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
{ 7F
70
{ 6F
60
{ 5F
50
{ 4F
40
{ 3F
30
{ 2F
20
{ 1F
10
{ 0F
00
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
The lower nibble of the
register file address provided
by the instruction points to
the specified register.
R15 to R0
R15 to R4 *
R3 to R0 *
* RP = 00: Selects Register Group 0, Working Register 0
Figure 18. Register Pointer—Detail
PS019402-1103
PRELIMINARY