Z89175 Datasheet, PDF (57/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
1 2 3 4 5 6 7 8 9 10 11
26 27 28 29 30 31 32
1
SCLK
2
P32
Input Sample
A/D Result
DSP INT
DSP Write
Notes:
1. SCLK = 10 MHz (XTAL =
20.48 MHz)
Figure 41. ADC Timing Diagram
Figure 42 shows the input circuit of the ADC. When con-
version starts, the analog input voltage from the input is
connected to the MSB and LSB flash converter inputs as
shown in the Input Impedance CKT diagram. Shunting 31
parallel internal resistances of the analog switches and si-
multaneously charging 31 parallel 1 pF capacitors is equiv-
alent to a 400 Ohms input impedance in parallel with a 31
pF capacitor. Other input stray capacitance adds about 10
pF to the input load. Input source resistances up to 2 kO-
hms can be used under normal operating conditions with-
out any degradation of the input settling time. For larger in-
put source resistance, longer conversion cycle times can
be required to compensate the input settling time problem.
V_REF is set using the V_REF + pin.
CMOS Switch
on Resistance
2-5kΩ
R Source
C Parasitic
V Ref
V Ref
V Ref
C .5 pF
C .5 pF
C .5 pF
31 CMOS Digital
Comparators
Figure 42. Input Impedance of ADC
DS97TAD0100
PRELIMINARY
57