Z89175 Datasheet, PDF (50/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
Field
Clear_IRQ1
Clear_IRQ0
Reserved
Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition
Position
-----------4----
------------3---
------------3---
-------------2--
-------------2--
--------------10
Attrib
W
R
W
R
W
W
R
Value
1
0
1
0
1
0
Label
Clear_IRQ2
Has_no_effect
Return "0"
Clear_IRQ1
No effect
Return "0"
Clear_IRQ0
No effect
No effect "0"
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 15). The bits are defined as fol-
lows:
DSP_IRQ2 (Z8 Interrupt). This bit is read by both Z8 and
DSP and is set only by writing to the Z8 expanded Register
File (Bank F, ROC, bit 0). This bit asserts IRQ2 of the DSP
and is cleared by writing to the Clear_IRQ2 bit.
LD ;
OR ;
POP ;
IRET ;
RP,#%0F
r12,#%01
RP
DSP Enable_INT. Writing a 1 to this location enables glo-
bal interrupts of the DSP while writing 0 disables them. A
system Reset globally disables all interrupts.
DSP_IRQ1 (A/D Interrupt). This bit is read by the DSP only
and is set when valid data is present at the A/D output reg-
ister (conversion done). This bit asserts IRQ1 of the DSP
and is cleared by writing to the Clear_IRQ1bit.
DSP_IRQ0 (D/A Interrupt). This bit is read by DSP only
and is set by Timer3. This bit assists IRQ0 of the DSP and
is cleared by writing to the Clear_IRQ0 bit.
DSP_MaskIntX. These bits are accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks off the corresponding
INT.
Z8_IRQ3. This bit can be read by both the Z8 and the DSP
but can only be set by the DSP. Addressing this location
accesses bit D3 of the Z8 IRQ register, hence, this bit is
not implemented in the ICR. During the interrupt service
routine executed on the Z8 side, the User must reset the
Z8_IRQ3 bit by writing a 1 to bit D0 of the DSPCON.
The hardware of the Z89175/176 automatically resets
Z8_IRQ3 bit three instructions of the Z8 after 1 is written to
its location in register bank 0F. This delay provides the tim-
ing synchronization between the Z8 and the DSP sides
during interrupts. In summary, the interrupt service routine
of the Z8 for IRQ3 should be finished by:
DSP_IPRX. This three-bit group defines the Interrupt Se-
lection logic as shown in Table 16.
Clear_IRQX. These bits are accessed by the DSP only.
Writing a 1 to these locations resets the corresponding
DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are
not implemented.
Table 16. DSP Interrupt Selection
DSP_IPR[2-0] Z8_INT is A/D_INT is D/A_INT is
2 1 0 switched to switched to switched to
000
001
010
011
100
101
110
111
INT2
INT1
INT2
INT1
INT0
INT0
Reserved
Reserved
INT1
INT2
INT0
INT0
INT2
INT1
Reserved
Reserved
INT0
INT0
INT1
INT2
INT1
INT2
Reserved
Reserved
50
PRELIMINARY
DS97TAD0100