Z89175 Datasheet, PDF (42/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
Zilog
Z8^® FUNCTIONAL DESCRIPTION (Continued)
Table 9. DSP Control Register (F) OCH [Read/Write]
Field
DSPCON (F)0CH
Z8_SCLK
DSP_Reset
DSP_Run
Reserved
Position
76------
--5-----
---4----
----32--
Attrib
R/W
R
W
R/W
W
R
Value
00
01
1x
0
1
0
1
DSP_INT2
------1-
R
W
1
0
Z8_IRQ3
-------0
R
W
1
0
Label
(OSC/8)
(OSC/4)
(OSC/2)
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
No effect
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
Z8 IRQ3 (D0). When read, this bit indicates the status of
the Z8 IRQ3. The Z8 IRQ3 is set by the DSP by writing to
D9 of DSP External Register 4 (ICR). By writing a 1 to this
bit, Z8 IRQ3 is Reset.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets the DSP INT2. Reading this bit indicates the
status of the DSP INT2.
DSP RUN (D4). This bit defines the HALT mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT mode, this bit is automatically pre-
set to 1. Writing a 0 has no effect.
Z8 SCLK (D7-D6). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both bits default to 00.
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 29). The WDTMR
register is accessible only within 64 Z8 clock cycles after
POR.
42
PRELIMINARY
DS97TAD0100