Z89175 Datasheet, PDF (24/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS
compatible port (Figure 12). It has multiplexed Address
(A7-A0) and Data (D7-D0) ports. These eight I/O lines are
programmed as inputs or outputs, or can be configured un-
der software control as an Address/Data port for interfac-
ing external memory. The input buffers are Schmitt-trig-
gered and the output drivers are push-pull.
Port 1 can be placed under handshake control. In this con-
figuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and /DAV1 (Ready and Data Avail-
Zilog
able). Memory locations greater than 24575 (Z89175) (in
ROM mode) are referenced through Port 1. To interface
external memory, Port 1 must be programmed for the mul-
tiplexed Address/Data mode. If more than 256 external lo-
cations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z89175/176
to share common resources in multiprocessor and DMA
applications.
8
Z89175/176
MCU
Port 1
(I/O or AD7 - AD0)
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
OEN
Out
In
24
1.5
2.3V Hysteresis
R = 500 kΩ
Figure 12. Port 1 Configuration
PRELIMINARY
Pad
Auto Latch
DS97TAD0100