Z89175 Datasheet, PDF (23/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
For external memory references, Port 0 provides address In ROMless mode, after a hardware reset, Port 0 is config-
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib- ured as address lines A15-A8, and extended timing is set
ble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
2
Port 0 can be programmed independently as I/O while the tended timing mode. (In ROM mode, Port 0 is defined as
lower nibble is used for addressing. If one or both nibbles input after reset.)
are needed for I/O operation, they are configured by writ-
ing to the Port 0 mode register.
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control sig-
nals /AS, /DS, and R//W (Figure 11).
4
Z89175/176
MCU
4
Port 0
(I/O or A15 - A8)
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Out
In
DS97TAD0100
1.5
2.3V Hysteresis
R = 500 KΩ
Figure 11. Port 0 Configuration
PRELIMINARY
Pad
Auto Latch
23