Z89175 Datasheet, PDF (49/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
Z8 Side
On the Z8, set D1 to
interrupt DSP via DSP INT2.
DSP CON
After serving IRQ3,
set D0 to clear the
interrupt request.
IRQ3 of the Z8
DSP Side
2
DSP INT2
10
After serving INT2,
set D4 to clear the
interrupt request.
9
4
ICR
(EXT4)
The DSP sets D9 to
interrupt Z8 via Z8 IRQ3.
Figure 34. Interprocessor Interrupts Structure
Field
DSP_IRQ2
DSP_IRQ1
DSP_IRQ0
DSP_MaskINT2
DSP_MaskINT1
DSP_MaskINT0
Z8_IRQ3
DSPintEnable
DSP_IPR2
DSP_IPR1
DSP_IPR0
Clear_IRQ2
Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition
Position
f---------------
f---------------
-e--------------
-e--------------
--d-------------
--d-------------
---c------------
----b-----------
-----a----------
------9---------
------9---------
-------8--------
--------7-------
---------6------
----------5-----
-----------4----
Attrib
R
W
R
W
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R
Value
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Binary
Binary
Binary
Label
Set_IRQ2
Reset_IRQ2
No effect
Set_IRQ1
Reset_IRQ1
No effect
Set_IRQ0
Reset_IRQ0
No effect
Enable_INT2
Disable_INT2
Enable_INT1
Disable_INT1
Enable_INT0
Disable_INT0
Return "0"
Set_Z8_IRQ3
Reset_Z8_IRQ3
Enable
Disable
IPR2
IPR1
IPR0
Return "0"
DS97TAD0100
PRELIMINARY
49