Z89175 Datasheet, PDF (51/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
DSP Analog Data Registers
A/D supplies 8-bit data to the DSP through the register
The D/A conversion is DSP driven by sending 10-bit data
to the EXT5 of the DSP. The six remaining bits of EXT5 are
not used (Figure 36).
EXT5 of the DSP. From the 16 bits of EXT5, only bits 2
through 9 are used by the A/D (Figure 37). Bits 0 and 1 are
padded with zeroes.
2
F E DCBA 9 8 7 6 5 4 3 2 1 0
Reserved
10-Bit Data for D/A
(Write Only)
Reserved
Figure 35. EXT5 Register D/A Mode Definition
F E D CBA 9 8 7 6 5 4 3 2 1 0
Reserved
8-Bit Data From A/D Converter
(Read Only)
Reserved
Figure 36. EXT5 Register A/D Mode Definition
Analog Control Register (ACR)
The Analog Control register is mapped to register EXT6 of
the DSP (Table 17). This read/write register is accessible
by the DSP only.
The 16-bit field of EXT6 defines modes of both the A/D and
the D/A. The High Byte configures the D/A while the Low
Byte controls the A/D mode.
Table 17. EXT6 Analog Control Register (ACR)
Field
Position
Attrib
MPX_DSP_INT0 f--------------- R/W
Value
1
0
Label
P26
Timer3
20.48
MHz
29.49
MHz*
Reserved
-edcba----------
R
W
Return “0”
No effect
Reserved
------9---------
R
W
Return “1”
No effect
D/A_SamplingRate-------8-------- R/W
0
1
16 kHz
10 kHz
8.04 kHz
9.6 kHz
DS97TAD0100
PRELIMINARY
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