Z89175 Datasheet, PDF (52/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
DSP REGISTERS DESCRIPTION (Continued)
Table 17. EXT6 Analog Control Register (ACR)
Field
Position
DSP_port (DSP1, --------76------
DSP0)
Attrib
R/W
Value
Label
User-defined DSP
outputs
20.48
MHz
Zilog
29.49
MHz*
Enable A/D
----------5----- R/W
1
A/D Enabled
0
A/D Disabled
ConversionDone -----------4----
W
R
No effect
1
Done
0
Not Done
StartConversion ------------3--- R/W
1
Start
0
Wait Timer
Reserved
-------------2--
R
W
Return “0”
No effect
20/29 MHz Select --------------1- R/W
1
29.49 MHz*
0
20.48 MHz†
A/D_SamplingRate---------------0 R/W
1
0
Notes:
* Default value
† Optional feature
16 kHz
8 kHz
16 kHz
9.6 kHz
DSP IRQ0. This bit defines the source of the DSP IRQ0 in-
terrupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A Sampling
Rate (Table 18).
Table 18. D/A Data Accuracy
D/A_Sampling Rate
Bit 8
0
1
Sampling Rate
20.48 MHz 29.49 MHz
16 kHz
10 kHz
8.04 kHz
9.6 kHz
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and can be used
to output data by writing to bit 6.
52
PRELIMINARY
DS97TAD0100