Z89175 Datasheet, PDF (22/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
PIN FUNCTIONS
/RESET (input, active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) reset, Stop-Mode Recov-
ery, or external reset. During POR and WDT Reset, the in-
ternally generated reset signal is driving the reset pin Low
for the POR time. Any devices driving the reset line must
be open-drain to avoid damage from a possible conflict
during reset conditions. A /RESET will reset both the Z8
and the DSP.
For the Z8: After the POR time, /RESET is a Schmitt-trig-
gered input. To avoid asynchronous and noisy reset prob-
lems, the Z8 is equipped with a reset filter of four external
clocks (4TpC). If the external reset signal is less than 4TpC
in duration, no reset occurs. On the fifth clock after the
/RESET is detected, an internal RST signal is latched and
held for an internal register count of 18 external clocks, or
for the duration of the external reset, whichever is longer.
Program execution begins at location 000CH (hexadeci-
mal), 5-10 TpC cycles after /RESET is released. The Z8
does not reset WDT, SMR, P2M, and P3M registers on a
Stop-Mode Recovery operation.
For the DSP: After POR, the DSP is in RUN mode. The Z8
controls the DSP commands to HALT, RUN or RESET.
When the DSP is in HALT mode, it cannot be woke up with
WDT or SMR.
RMLS ROMless (input, active High). This pin, when con-
nected to VDD, disables the internal Z8 ROM. (Note that,
when pulled Low to GND, the device functions normally as
the ROM version.) The DSP cannot be configured as
ROMless. This pin is only available on the Z89175.
R//W Read/Write (output, write Low). The R//W signal de-
fines the signal flow when the Z8 is reading or writing to an
external program or data memory. The Z8 is reading when
this pin is High and writing when this pin is Low.
/AS Address Strobe (output, active Low). Address Strobe
is pulsed once at the beginning of each machine cycle. Ad-
dress output is through Port 0/Port 1 for all external pro-
grams. Memory address transfers are valid at the trailing
edge of /AS. Under program control, /AS is placed in the
high-impedance state along with Ports 0 and 1, Data
Strobe, and Read/Write.
/DS Data Strobe (output, active Low). Data Strobe is acti-
vated once for each external memory transfer. For read
operations, data must be available prior to the trailing edge
of /DS. For write operations, the falling edge of /DS indi-
cates that output data is valid.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC net-
work, or an external single-phase clock to the on-chip os-
cillator input.
Zilog
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, or LC network
to the on-chip oscillator output.
DSP0 (output). DSP0 is a general-purpose output pin con-
nected to bit 6 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to out-
put data by writing to bit 6 of the ACR.
DSP1 (output). DSP1 is a general-purpose output pin con-
nected to bit 7 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to out-
put data by writing to bit 7 of the ACR.
PWM Pulse Width Modulator (Output). The PWM is a 10-
bit resolution D/A converter. This output is a digital signal
with CMOS output levels.
AN_IN (input). Analog input for the A/D converter.
ANV_DD. Analog power supply for the A/D converter.
VREF+ (input). Reference voltage (High) for the A/D con-
verter.
V_DD. Digital power supply for the Z89175.
GND. Digital ground for the Z89175.
OSC1 Oscillator 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC net-
work to the on-chip oscillator input.
OSC2 Oscillator 2 (time-based output). This pin connects
a parallel-resonant crystal, ceramic resonator, LC, RC net-
work to the on-chip oscillator output.
NC No Connect. For the 100-pin QFP package, pins 63
through 76, and pins 78 and 79 should be tied to Ground.
Other NC pins must float.
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured un-
der software control as a nibble I/O port, or as an address
port for interfacing external memory. The input buffers are
Schmitt-triggered and the output drivers are push-pull.
Port 0 is placed under handshake control. In this configu-
ration, Port 3, lines P32 and P35 are used as the hand-
shake control /DAV0 and RDY0. Handshake signal direc-
tion is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same di-
rection as the upper nibble.
The Auto Latch on Port 0 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1 cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply cur-
rent flow in the input buffer.
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PRELIMINARY
DS97TAD0100