Z89175 Datasheet, PDF (53/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
DSP1. DSP1 is a general-purpose output pin connected to input data is converted upon successive Timer2 time-outs.
Bit 7. This bit has no special significance and can be used A hardware reset forces this bit to 1.
to output data by writing to bit 7.
2 ^{A/D_Sampling Rate. This field defines the sampling rate}
Enable A/D. Writing a 0 to this location disables the A/D of the A/D. It changes the period of Timer2 interrupt (Table
converter, a 1 will enable it. A hardware reset forces this 19).
bit to 0.
Table 19. A/D Sampling Rate
Conversion Done. This Read-Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D da-
A/D_Sampling Rate
Sampling Rate
ta), the Conversion Done flag is cleared.
Bit 0
20.48 MHz 29.49 MHz
1
Start A/D Conversion. Writing a 1 to this location immedi-
ately starts one conversion cycle. If this bit is reset to 0 the
0
16 kHz
8 kHz
16 kHz
9.6 kHz
DSP TIMERS
Timer2 is a free running counter that divides the XTAL fre-
quency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the An-
alog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
Analogous to Timer2, Timer3 generates the different sam-
pling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 37).
Timer2
8, 16 kHz
A/D
OSC
20.48 MHz
Timer3
16, 10 kHz
D/A
Timer2
16, 9.6 kHz
A/D
USC
29.49 MHz
Timer3
8.04, 9.6 kHz
D/A
Figure 37. Timer2 and Timer3
DS97TAD0100
PRELIMINARY
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