Z89175 Datasheet, PDF (40/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
Z8^® FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 26). All bits are Write-Only
except bit 7, which is Read-Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
Zilog
a high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4, or the
SMR register, specify the source of the Stop-Mode Recov-
ery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR is located in Bank F of the Expanded Reg-
ister group at address 0BH.
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
† Reset After Stop-Mode Recovery
W 0 SCLK/TCLK not divided by 16†
1 SCLK/TCLK divided by 16
R Always "1"
Reserved
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 Half second timeout from
33 kHz ext. osc.
110 P2 NOR 0-3
111 P2 NOR 0-7
R Always "1"
W Stop Delay
0 OFF
1 ON*
R Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
1 Stop-Mode Recovery
Figure 26. Stop-Mode Recovery Register (SMR)
40
PRELIMINARY
DS97TAD0100