Z89175 Datasheet, PDF (48/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
DSP Interrupts
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 33). These sources have different pri-
ority levels (Figure 34). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
Zilog
and INT0, respectively (Figure 35). The DSP does not al-
low interrupt nesting (interrupting service routines that are
currently being executed). When two interrupt requests oc-
cur simultaneously the DSP starts servicing the interrupt
with the highest priority level.
Z8_INT
A/D INT
D/A INT
IPR2
IPR1
IPR0
FB DSP
Interrupt Priority Logic
Interrupt Request Logic
FeedBack Z8_INT MPX
INT2
INT1
INT0
Interrupt Mask Logic
INT2
INT1
INT0
CLEAR_INT0
CLEAR_INT1
CLEAR_INT2
ENABLE_INT
Figure 32. DSP Interrupts
INT0
INT1
INT2
DSP Execution
INT2
INT0
INT1
INT2
Figure 33. DSP Interrupt Priority Structure
48
PRELIMINARY
DS97TAD0100