Z89175 Datasheet, PDF (39/68 Pages) Zilog, Inc. – Voice Processing Controllers

Zilog
Z89175/Z89176
Voice Processing Controllers
Port Configuration Register (PCON). The PCON regis- Power-On Reset (POR). A timer circuit clocked by a ded-
ter configures the comparator output on Port 3. The PCON icated on-board RC oscillator is used for the Power-On Re-
2 ^{register (Figure 25) is located in the Expanded Register set (POR) timer function. The POR time allows VCC and}
File at Bank F, location 00H.
the oscillator circuit to stabilize before instruction execu-
tion begins.
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator use in Port 3. A 1 in this location brings the com- The POR timer circuit is a one-shot timer triggered by one
parator outputs to P34 and P35, and a 0 releases the Port of three conditions:
to its standard I/O configuration.
1. Power fail to Power OK status;
PCON (F) %00
D7 D6 D5 D4 D3 D2 D1 D0
Note: Reset condition is 11111110
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
R Always "1"
W No effect
Figure 25. Port Configuration Register (PCON)
Port 4 and 5 Configuration Register (P45CON). The
P45CON register configures Port 4 and Port 5, individual-
ly, to open-drain or push-pull active. This register is located
in the Expanded Register File at Bank F, location 06H (Fig-
ure 26).
Port 4 Open-Drain (D0). Port 4 can be configured as an
open-drain by resetting this bit (D0 = 0) or configured as
push-pull active by setting this bit (D0 = 1). The default val-
ue is 1.
Port 5 Open-Drain (D4). Port 5 can be configured as an
open-drain by resetting this bit (D4 = 0) or configured as
push-pull active by setting this bit (D4 = 1). The default val-
ue is 1.
2. Stop-Mode Recovery (if D5 of SMR=1);
3. WDT time-out.
The POR time is a nominal 5 ms. Bit 5 of the STOP mode
register determines whether the POR timer is bypassed af-
ter Stop-Mode Recovery (typical for external clock, RC/LC
oscillators).
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts, either externally or inter-
nally generated.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation. It reduces the standby current to
20 µA or less. The STOP mode is terminated by a reset
only, either by WDT time-out, POR, SMR, or external re-
set. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate Sleep instruction, i.e.,
FF
NOP
; clear the pipeline
6F
STOP
; enter Stop mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter Halt mode
DS97TAD0100
PRELIMINARY
39