Z89175 Datasheet, PDF (2/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
GENERAL DESCRIPTION (Continued)
Z8 Core Processor
The on-chip Z8 is Zilog’s 8-bit microcontroller core with an
Expanded Register File to allow access to register-
mapped peripheral and I/O circuits. The Z8 offers a flexible
I/O scheme, an efficient register and address space struc-
ture and a number of ancillary features which makes it ide-
ally suited for high-volume processing, peripheral control-
lers and consumer applications.
For applications demanding powerful I/O capabilities, the
Z89175 provides 47 pins dedicated to input and output.
These I/O lines are grouped into six ports. Each port is
configurable under software control to provide timing, sta-
tus signals and parallel I/O with or without handshake.
Four basic memory resources for the Z8 are available to
support a wide range of configurations: Program Memory,
Register File, Data Memory, and Expanded Register File.
The Z8 core processor is supported by an efficient register
file that allows any of 256 on-board data and control regis-
ters to be either the source and/or the destination of almost
any instruction. This unique architecture eliminates tradi-
tional microprocessor Accumulator bottlenecks and per-
mits rapid content switching.
The Register File is composed of 236 bytes of general-pur-
pose registers, four I/O port registers, and 15 control and
status registers. The Expanded Register File consists of
mailbox registers, WDT mode register, DSP Control regis-
ter, Stop-Mode Recovery register, Port Configuration reg-
ister, and the control and data registers for Port 4 and Port
5. Some of these registers are shared with the DSP.
To unburden the software from supporting real-time prob-
lems such as counting/timing and data communication, the
Z8 offers two on-chip counter/timers with a large number
of user-selectable modes.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power op-
eration. The low-power Stop Mode allows parameter infor-
mation to be stored in the register file if power fails. An ex-
ternal capacitor or battery will retain device memory and
power the 32 kHz timer.
Zilog
DSP Coprocessor
The DSP coprocessor is a second generation, 16-bit two’s
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are ac-
complished in a single clock cycle. The processor contains
two on-chip data RAM blocks of 256 words, a 8K word pro-
gram ROM, 24-bit ALU, 16x16 multiplier, 24-bit Accumula-
tor, shifter, six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of four pointers which can be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be simul-
taneously addressed and loaded to the multiplier for a true
single-cycle scalar multiply.
Four external DSP registers are mapped into the expand-
ed register file of the Z8. Communication between the Z8
and the DSP occurs through those common registers
which form the mailbox registers.
The analog output is generated by a 10-bit resolution
Pulse Width Modulator. The PWM output is a digital signal
with CMOS output levels. The output signal has a resolu-
tion of 1 in 1024 with a sampling rate of 16 kHz (XTAL =
20.48 MHz). The sampling rate can be changed under
software control and can be set at 10 and 16 kHz. The dy-
namic range of the PWM is from 0 to 4V.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
16 kHz. (XTAL = 20.48 MHz) in order to provide oversam-
pling. The input signal is 4V peak to peak.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free-running counters
that divide the crystal frequency to the appropriate sam-
pling of frequency. Two DSP I/O pins: DSP0, DSP1 are
provided for application.
2
PRELIMINARY
DS97TAD0100