Z89175 Datasheet, PDF (36/68 Pages) Zilog, Inc. – Voice Processing Controllers

Z89175/Z89176
Voice Processing Controllers
Z8^® FUNCTIONAL DESCRIPTION (Continued)
Table 6. Interrupt Types, Sources, and Vectors
Name
Source
Vector
Location
Comments
IRQ0 /DAV0, P32,
AN2
IRQ1 /DAV1, P33
IRQ2 /DAV2, P31,
TIN, AN2
IRQ3
IRQ3
IRQ4
T0
IRQ5
TI
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
External (P32),
Programmable Rise
or Fall Edge
Triggered
External (P33), Fall
Edge Triggered
External (P31),
Programmable Rise
or Fall Edge
Triggered
Internal (DSP
activated), Fall Edge
Triggered
Internal
Internal
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder controlled by
the Interrupt Priority Register. An interrupt machine cycle
is activated when an interrupt request is granted. This dis-
ables all subsequent interrupts, pushes the Program
Counter and Status Flags to the stack, and then branches
to the program memory vector location reserved for that in-
terrupt.
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register can be polled to determine
which of the interrupt requests needs service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 can be rising, falling or both edge trig-
gered, and are programmable by the user. The software
can poll to identify the state of the pin.
Zilog
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configu-
ration is shown in Table 7.
Table 7. IRQ Register
IRQ
D7
D6
0
0
0
1
1
0
1
1
Notes:
F = Falling Edge
R = Rising Edge
Interrupt Edge
P31
P32
F
F
F
R
R
F
R/F
R/F
Clock. The Z89175/176 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The system clock
(SCLK) is one half the crystal frequency.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to Ground (Figure 23).
36
PRELIMINARY
DS97TAD0100