DS543 Datasheet, PDF (9/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Memory Mapped Registers
The Memory Mapped Register (MM_REG) module contains all registers for control and status of the
MOST NIC. All registers are 32-bits wide. For detailed information about the MOST NIC programming
and status registers and information about programming them, see "Chapter 6, Configuration Space," and
"Chapter 7, Programming the Core," in the MOST NIC User Guide.
Clocking and Reset
Clocking
The MOST Controller contains three input clocks: MOST Clocks (MOST_PLL_CLK, MOST_COM_CLK)
and OPB Clock (OPB_Clk). The following conditions apply to clock frequencies:
• MOST_PLL_CLK and MOST_COM_CLK can be either 45.1584 MHz or 49.152 MHz and are frequency-
locked to each other.
• OPB_Clk is asynchronous to the MOST clocks, and may have a minimum clock frequency of 0.7
times the MOST_PLL_CLK. The maximum will depend on the device selected, but all devices will
allow at least 75 MHz. The requirements for the DCM must also be met.
• An external clock source is required for Master and Loopback modes.
• An external clock and data recovery PLL is required for MOST_PLL_CLK operation.
• The streaming port clock (STR_CLK) is an output and identical to the OPB Clock, where the core
forwards this clock on behalf of the user.
Reset Mechanism
Two reset mechanisms are provided for the MOST NIC: the OPB_Rst input is a hard reset (Table 5), and
a software-controlled soft reset is provided through a user configuration register. Both the hard and soft
resets cause all logic within the MOST NIC to return to the default state.
Hard Reset
Assertion of OPB_Rst causes all logic within the MOST NIC to return to the default state. All configu-
ration registers not located in block RAM are returned to their default values as indicated in the mem-
ory map description. Read/Write transactions cannot be performed while the OPB_Rst input is
asserted.
Soft Reset
Assertion of the soft reset signal causes all logic within the MOST NIC to return to the default state. All
configuration registers not located in block RAM with the exception of the soft reset control register are
returned to their default values as indicated in the memory map description. Read/Write OPB transac-
tions can be performed starting at the next valid transaction window.
DS543 September 19, 2008
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