DS543 Datasheet, PDF (3/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Streaming Port
The MOST NIC core supports a streaming port that provides access to the synchronous data portion of
the MOST stream in real time without requiring processing by the host. This port allows both ingress
(write to the NIC) and egress (read from the NIC) transactions. Both transmit and receive data can be
accessed by logical channel (see below for more information about logical channels). The data is avail-
able per byte for this Xilinx LocalLink interface.
• Receive. The Receive Streaming port can be used to optionally intercept and/or insert data into the
MOST NIC receive path. This allows for additional processing of the data where the external
module can act as a sink, source, or a preprocessor of the stream, offloading operations from the
host.
• Transmit. Similarly, the Transmit Streaming port can be used to optionally intercept and/or insert
data into the MOST NIC transmit path. This allows for additional processing of the data where the
external module can act as a sink, source, or a preprocessor of the stream, offloading operations
from the host.
• Register Control. The MOST NIC core contains dedicated memory-mapped register space for the
streaming port. Any accesses to these locations is forwarded to the streaming port. The external
module can then implement control registers, accessible through the MOST NIC core. Typical
applications for the streaming port are synchronous data encryption and decryption.
Logical Channel Mapping
Audio or video data is typically spread over several synchronous timeslots, and as such, grouping
related timeslots into a logical channel is efficient for software processing. The MOST NIC core groups
physical timeslot data into logical channel data under user control and automatically synchronizes the
multiple timeslots on a per-frame basis. The MOST NIC core contains 32 logical channel buffers: sixteen
reserved for transmit operations, and sixteen for receive operations. A logical channel can aggregate
from one to 60 time slots in any of the synchronous physical channels or can be mapped to the asyn-
chronous channel.
For the receive path, 4 logical channels are dedicated to streaming port ingress access, 4 logical channels
for streaming port egress, and 8 logical channels for OPB receive. Similarly, for the transmit path, 4 logical
channels are dedicated to streaming port ingress access, 4 logical channels for streaming port egress, and
8 logical channels for OPB transmit. Logical channel # 0 is reserved for asynchronous data in both direc-
tions.
Each logical channel buffer is capable of storing up to 32 words of 32-bits each. All buffers can assert
interrupts to an external microprocessor to indicate that the buffer requires processing. The word count
at which the interrupt is asserted is configurable by the user.
The MOST NIC core provides a host interface for access to control and status registers. The interface is
a 32-bit wide OPB bus. The OPB bus is also used to transfer transmit data and receive MOST frame
data.
Loopback
The transmit path can be internally connected to the MOST controller receive path for diagnostic tests,
allowing the user to receive all frames transmitted. A user can validate that the configuration of the
core and the data path are as expected before insertion on the MOST ring.
DS543 September 19, 2008
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