DS543 Datasheet, PDF (1/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

DS543 September 19, 2008
MOST Network Interface
Controller v1.4
Product Specification
Introduction
The LogiCORE™ Media Oriented Systems Transport
Network Interface Controller (MOST^® NIC) core is a
complete controller designed to the MOST Specification
revision 2.4. When combined with the Xilinx Automo-
tive (XA) solution and embedded processing, the
MOST NIC core lets designers leverage the MOST open
standard network by providing a higher level of cus-
tomization in a scalable, flexible design solution.
Features
• Operates in both master and slave modes
• Full bandwidth sustained transfers (24 Mbps)
• Supports full control channel bandwidth utilizing
two transmit and receive buffers
• Synchronous, asynchronous, and control channels
with 4-60 bytes of synchronous data per frame
• Flexible user interfaces
- 32-bit OPB interface allows use in Xilinx EDK
- LocalLink-based streaming port for real-time data
access
• Physical to logical channel mapping performed in
hardware with 16 transmit and 16 receive logical
channels available to the user
• Parameterizable
- Provision to select master/slave
- Word count triggers for egress/ingress channel
buffers
• Full support of error and status notification
• Internal loopback mode for diagnostic applications
• Support for Ring Break Diagnosis (RBD) test
• MicroBlaze™, PowerPC® driver, and network
services from MOCEAN® Laboratories, AB
(MOCEAN)
• Low-cost recovery PLL available from Integrated
Device Technology, Inc. (IDT®)
• Available through the Xilinx CORE Generator™
LogiCORE Facts
Core Specifics
Supported Device
Family
Spartan®-3/XA, Spartan-3E/XA,
Spartan-3A, Spartan-3AN,
Spartan-3A DSP,
Virtex®-II Pro, Virtex-4
Resources Used
I/O
LUTs
FFs
Block
RAMs
7
4450- 2620-
4590 2670
6
OPB Performance
At least 75 MHz in all supported
devices
Ring Performance
44.1 kHz and 48 kHz frame
rates supported
Provided with Core
Documentation
Product Specification
Getting Started Guide
User Guide
Release Notes
Design File Formats
VHDL and Verilog®
Constraints File
UCF
Verification
VDHL and Verilog Test Bench
Instantiation Template
VHDL and Verilog
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 10.1
Simulation
Mentor Graphics® ModelSim® v6.3c
Cadence® IUS 6.1
Synthesis
XST
Support
Provided by Xilinx, Inc. @ www.xilinx.com/support
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DS543 September 19, 2008
www.xilinx.com
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