DS543 Datasheet, PDF (13/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 4: MOST Ring Interface (Cont’d)
Signal Name
Direction
Description
MOST_EXT_NRESET
Output
MOST External Not-Reset: This active low signal can be used to drive
a reset externally to the core. It is suggested to connect this to the reset
of the PLL, in order to reset the PLL directly from software.
MOST_EXT_BYPASS
Output
MOST External Bypass: This signal can be used to control the state
of the external PLL by placing it into bypass mode. This signal is not
related to the programming of the MODE select register.
MOST_FOR_STATUS
Input
Fiber Optic Receiver Status: Indicates availability of the external
FOR.
MOST_PLL_LOCK
Input
PLL Lock: The external PLL lock status negates this signal to indicate
the receive clock is locked. This connection is not mandatory as the
core examines the quality of the input clock to detect a loss of lock.
MOST_MASTER
Output
MOST Master: Indicates if this node is acting as the master. This is
used to control the input of the off chip PLL to be either the RX line (for
acting slaves) or an off chip crystal (for acting masters). This is
applicable for master configured nodes as well as slaves in Ring Break
Diagnostics acting as a master.
Host Interface
Table 5 defines the MOST host interface signals (OPB_*/Sln_*). The MOST NIC contains a 32-bit OPB
slave interface bus to interface to the PowerPC, MicroBlaze, or other microprocessors. There are sepa-
rate read and write data buses with a shared address bus. The host interfaces is used to access control
registers as well as transmit / receive data.
Byte Enable Functionality
The MOST NIC core implements a superset of the standard OPB interface with regards to byte enables.
All OPB accesses are considered long word aligned accesses, that is, bits 0 and 1 of the address are
ignored, and assumed to be 00b. The byte enable signals are used to qualify which byte(s) are selected
within the long word access.
If OPB_BE[0] is asserted, OPB_DBus[0:7] are selected for access
If OPB_BE[1] is asserted, OPB_DBus[8:15] are selected for access
If OPB_BE[2] is asserted, OPB_DBus[16:23] are selected for access
if OPB_BE[3] is asserted, OPB_DBus[24:31] are selected for access
The OPB_BE[0:3] bus can be driven with any value from 0x0 to 0xF.
Burst Support
The OPB interface accepts both burst and single cycle transactions to the control registers. However,
only the TX Buffer (TXBUFF), RX Buffer (RXBUFF), Common Routing Table (CRT), and Master Alloca-
tion Tables (MAT) provide optimized pipelined data acknowledgement for burst requests. Burst
requests to all other registers are treated as consecutive single-cycle access.
DS543 September 19, 2008
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