DS543 Datasheet, PDF (16/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 6: MOST Streaming Port Interface (Cont’d)
Signal Name
Direction
Description
STR_MMR_BE[0:3]
Output
Memory Map Byte Enable: Selects which byte lane of the data bus is
being accessed.
STR_MMR_WDATA[0:31]
Output
Memory Map Write Data: The data being written to the streaming port.
Asserted coincident with STR_MMR_REQ. The STR_MMR_WDATA
signals will remain constant during the memory map access. This signal
is only valid when MMR_RNW = ’0.’
STR_MMR_RDATA[0:31]
Input
Memory Map Read Data: Data read from the streaming port external
module. Data is valid when a read request followed by an
acknowledgment STR_MMR_ACK is asserted
STR_MMR_ACK
Input
Memory Map Acknowledge: Asserted by the target to indicate
completion of a write or read cycle. When asserted the cycle is
complete and returned read data is latched. The STR_MMR_REQ
signal is deasserted immediately after assertion of ACK to complete
the transaction.
STR_MMR_INT
Input
Interrupt In: The target asserts this signal for 1 clock duration to set
the MOST interrupt status register bit assigned to the streaming port.
If enabled this will cause an interrupt to the external microprocessor.
The STR_MMR_INT signal must be asserted for 1 clock duration only.
Data Transfer: Receive Streaming Port–Egress
STR_RE_LC[0:1]
Input
Receive Egress Logical Channel: Logical channel for the data being
requested
STR_RE_DATA [0:7]
Output
Receive Egress Data: Data read from to the logical channel selected
on STR_RE_LC. Data is valid when a read request followed by an
acknowledgment by requestor (SRC_RDY) and target (DST_RDY) is
asserted
STR_RE_BIF_AVAIL[0:3]
Output
Receive Egress Buffer Interface Available: When asserted, data is
available in the given logical channel buffer. This signal is deasserted
when the core is not enabled and triggers low in the event of the logical
channel flush from the Host Interface.
STR_RE_SRC_RDY
Output
Receive Egress Source Ready: Read data on the STR_RE_DATA is
available and valid.
STR_RE_DST_RDY
Input
Receive Egress Destination Ready: The requestor is ready for data
for this logical channel (STR_RE_LC)
STR_RE_WCINT[0:3]
Output
Receive Egress Interrupt: Asserted for 1 clock when the receive
egress logical channel buffer has crossed the word count as
configured by the full word count parameter (FWC). There is one signal
for each receive read logical channel.
Data Transfer: Receive Streaming Port–Ingress
STR_RI_LC[0:1]
Input
Receive Ingress Logical Channel: Logical channel for the data being
written.
STR_RI_DATA[0:7]
Input
Receive Ingress Data: Data being written the logical channel selected
on STR_RI_LC. Data is accepted when a write request followed by an
acknowledgment by requestor (SRC_RDY) and target (DST_RDY) is
asserted
16
www.xilinx.com
DS543 September 19, 2008