DS543 Datasheet, PDF (7/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Functional Overview
The MOST NIC core is a full-featured soft IP core incorporating all necessary logic to interface to a
MOST ring. The core supports the transmission and reception of synchronous, asynchronous, and con-
trol data to and from the MOST ring.
Module Architecture
Figure 4 illustrates the major sub-modules of the MOST NIC.
Figure Top x-ref 4
RX Egress
RX Ingress
MOST RX
RX_REC
RX_MAC
RX_RE
TS,
ASYNC
to
LC
RX_BUF
By LC
CONTROL
State
Machine
COM_ROUTE
block
RAM
MM_REG
block
RAM
Reg
OPB
MOST TX
TX_BYPASS
TX_MAC
TX_RE
LC to TS
ASYNC
TX_BUF
By LC
TX Ingress
TX Egress
Figure 4: MOST NIC Block Diagram
Receive Recovery
The Receive Recovery (RX_REC) module realigns the incoming MOST data to the recovered/corrected
MOST clock from the off-chip PLL.
Receive MAC
The Receive MAC (RX_MAC) module decodes the received MOST frame. It has several functions
including frame decode, serial-to-parallel conversion, and timing decode.
DS543 September 19, 2008
www.xilinx.com
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