DS543 Datasheet, PDF (15/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Streaming Port
Table 6 defines the MOST NIC steaming port signals (STR_*). The streaming port has five main com-
ponents: the Memory Map Register and the four Data Transfer interfaces.
Memory Map Register
A subset of the MOST NIC memory map is reserved for the streaming port. Access to these locations
are forwarded to the streaming port. An external module interface to the streaming port can then
implement control register specific to that module (but accessed through the MOST NIC memory map).
This group also contains an interrupt port such that the external module can assert an interrupt source
within the MOST NIC.
Data Transfer
The MOST NIC core includes one receive and one transmit streaming port based on the LocalLink
interface for data transfer. The streaming ports are used to access synchronous channel data in the
transmit and receive FIFOs on a logical channel basis. Both the transmit and receive streaming ports
have ingress and egress capabilities.
As a general rule, the logical channel width is 4 bits. However, for the streaming ports, the logical chan-
nels are split by port type. Internal to the core, all egress logical channel values have a prefix of 11b and
all ingress logical channel values have a prefix of 10b.
The streaming port contains interrupt signals to indicate logical channel buffer word count status. The
word count interrupt signals indicate when the logical channel buffers have enough data to be pro-
cessed, as defined by the full and empty word count parameters in Table 1, “Word Count Parameters,”
on page 10. The interrupt is a one-clock wide active high pulse synchronous to the STR_CLK.
The interrupts are generated by this controller and processed as required by the external module. In the
case of egress buffers, an interrupt is asserted when there is sufficient data in the FIFO that can be read
by the streaming port. In the case of ingress buffers, an interrupt is asserted when there is sufficient free
space in the FIFO to allow for additional write data from the streaming port.
Table 6: MOST Streaming Port Interface
Signal Name
Direction
Description
Common to All Interfaces
STR_CLK
Output Clock: All signals on the streaming port are synchronous to this clock
STR_RST
Output
Reset: An active high reset signal that is asserted when ever the
MOST core is reset (by either hard or soft reset)
Memory Map
STR_MMR_REQ
Output
Memory Map Request: Assertion indicates an active read or write to
the streaming port memory mapped signals. The REQ signal qualifies
all other streaming port memory map signals. The REQ signal is
deasserted when the transfer is complete (STR_MMR_ACK) sampled
high.
STR_MMR_RNW
Output
Memory Map Read / Write: Indicates the direction of the memory map
transfer. Logic ’1’ indicates reads. Logic ’0’ indicates writes. Asserted
coincident with STR_MMR_REQ. The STR_MMR_RNW signal must
remain constant during the memory map access.
STR_MMR_ADDR[0:7]
Output Memory Map Address: The address being written to or read from.
DS543 September 19, 2008
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