DS543 Datasheet, PDF (17/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 6: MOST Streaming Port Interface (Cont’d)
Signal Name
Direction
Description
STR_RI_BIF_AVAIL[0:3]
Output
Receive Ingress Buffer Interface Available: When asserted, data is
available in the given logical channel buffer. This signal is deasserted
when the core is not enabled and triggers low in the event of the logical
channel flush from the Host Interface.
STR_RI_SRC_RDY
Input
Receive Ingress Source Ready: Write data on the STR_RI_DATA is
available and valid.
STR_RI_DST_RDY
Output
Receive Ingress Destination Ready: The target has accepted the
write data for this logical channel (STR_RI_LC)
STR_RI_WCINT[0:3]
Output
Receive Ingress Interrupt: Asserted for 1 clock when the receive
ingress logical channel buffer has crossed the word count as
configured by the empty word count parameter (EWC). There is one
signal for each receive write logical channel.
Data Transfer: Transmit Streaming Port–Egress
STR_TE_LC[0:1]
Input
Transmit Egress Logical Channel: Logical channel for the data
being requested
STR_TE_DATA [0:7]
Output
Transmit Egress Data: Data read from the logical channel selected
on STR_TE_LC. Data is valid when a read request followed by an
acknowledgment by requestor (SRC_RDY) and target (DST_RDY) is
asserted
STR_TE_BIF_AVAIL[0:3]
Output
Transmit Egress Buffer Interface Available: When asserted, data is
available in the given logical channel buffer. This signal is deasserted
when the core is not enabled and triggers low in the event of the logical
channel flush from the Host Interface.
STR_TE_SRC_RDY
Output
Transmit Egress Source Ready: Read data on the STR_TE_DATA is
available and valid.
STR_TE_DST_RDY
Input
Transmit Egress Destination Ready: The requestor is ready for data
for this logical channel (STR_TE_LC)
STR_TE_WCINT[0:3]
Output
Transmit Egress Interrupt: Asserted for 1 clock when the transmit
egress logical channel buffer has crossed the word count as
configured by the full word count parameter (FWC). There is one signal
for each transmit read logical channel
Data Transfer: Transmit Streaming Port–Ingress
STR_TI_LC[0:1]
Input
Transmit Ingress Logical Channel: Logical channel for the data
being written
STR_TI_DATA[0:7]
Input
Transmit Ingress Data: Data being written to the logical channel
selected on STR_TI_LC. Data is accepted when a write request
followed by an acknowledgment by requestor (SRC_RDY) and target
(DST_RDY) is asserted
STR_TI_BIF_AVAIL[0:3]
Output
Transmit Ingress Buffer Interface Available: When asserted, data is
available in the given logical channel buffer. This signal is deasserted
when the core is not enabled and triggers low in the event of the logical
channel flush from the Host Interface.
DS543 September 19, 2008
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