DS543 Datasheet, PDF (20/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 7: MOST Controller Registers (Cont’d)
Name
Register
Name
Byte
Enable
Description
Flush Control
FCR
Y
Register allows the Synchronous, Asynchronous and Control Buffers
to be flushed.
Transmit Buffer
Error
TXBER
N
Indicates which transmit logical channel buffers have underflow or
overflow errors.
Receive Buffer
Error
RXBER
N
Indicates which receive logical channel buffers have underflow or
overflow errors.
MOST Control Processing
Message Retry
Count and Delay
MRCDR
Contains the retry count and delay value for the re-transmission of the
Y
control messages. The count value configures how many times the
re-transmission should take place and the delay value configures the
gap between the re-transmission.
Control Transmit
Status
CTXS
Y
Register contains status and control for the transmission of control
messages.
Control Receive
Status
CRXS
N
Register contains status and control for the reception of control
messages.
Control Transmit
FIFO
CTXFIFO
A write buffer used to add control messages for transmission. Control
messages can be 2 to 6 words in length. The control transmit
N
message FIFO contains sufficient storage to hold one complete
message. The control module within the core will also queue a
message, for a total storage ability of 2 messages. The FIFO is
accessed by writing words sequentially to the CTXFIFO.
Control Transmit
Response FIFO
CTXRESFIFO
A read buffer used to read transmit message responses and status.
Control messages can be up to from 2 to 6 words in length. A seventh
N
word is used to return the transmission status. The control transmit
response FIFO contains sufficient storage to hold one complete
message, including the request, response and status. The buffer is
accessed by reading words sequentially from the CTXRESFIFO.
Control Receive
FIFO
CRXFIFO
A read buffer used to read received control messages. Control
messages can be up to from 2 to 6 words in length. The control
N receive message FIFO contains sufficient storage to hold two
complete messages. The buffer is accessed by reading words
sequentially from the CRXFIFO.
Interrupt Status/Control
MOST Interrupt
Status
MISR
Contains bits that are set when a particular interrupt condition occurs.
Y If the corresponding mask bit in the MOST Interrupt Enable Register
(MIER) is set, an interrupt is generated.
MOST Interrupt
Pending
MIPR
N
Indicates the interrupts that are actually indicated to software. In
effect, it is the MISR register bit wise ANDed with the MIER register.
MOST Interrupt
Enable
MIER
Y
Used to enable or disable the generation of the interrupts. Interrupts
are enabled by setting the appropriate bit in the MIER.
MOST Interrupt
Clear
MICR
Used to clear interrupt status bits. Writes of ’1’ clear the appropriate
Y bit in the MOST Interrupt Status Register (MISR) and
correspondingly the MOST Interrupt Pending Register (MIPR).
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DS543 September 19, 2008