DS543 Datasheet, PDF (22/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 7: MOST Controller Registers (Cont’d)
Name
Register
Name
Byte
Enable
Description
Transmit/Receive Buffer
Transmit Buffer
TXBUFF
This portion of the memory map allows for FIFO based access to the
transmit buffers. The transmit buffer is organized on a logical channel
basis. The transmit buffer supports a total of 16 logical channels.
N
Each buffer contains 32 words. To ease in programming the Logical
Channel # forms the 3rd Most Significant Nibble of the Transmit Buffer
Address. As such the address space supports 64 words per logical
channel. However, each logical channel FIFO is only 32 words deep.
Figure 5 illustrates the memory map with respect to channel type.
Receive Buffer
RXBUFF
This portion of the memory map allows for FIFO based access to the
receive buffers. The receive buffer is organized on a logical channel
basis. The receive buffer supports a total of 16 logical channels. Each
N
buffer contains 32 words. To ease in programming the Logical
Channel # forms the 3rd Most Significant Nibble of the Receive Buffer
Address. As such the address space supports 64 words per logical
channel. However, each logical channel FIFO is only 32 words deep.
Figure 5 illustrates the memory map with respect to channel type.
Resource Utilization and Performance
The MOST NIC core can be generated in several configurations to provide maximum flexibility for spe-
cific user applications. For this reason, resource utilization depends on the core configuration selected
by the user. Table 8 provides sample resource utilization numbers for the MOST NIC core. The most
effective method for determining resource requirements for a user application is to generate a core with
the required feature set, and then run the provided implementation script.
Table 8: MOST NIC Core Resource Utilization
Configuration
Maximum: Full Master/Slave core, word counts set to 16
Minimum: Slave only core, word counts set to 8
LUTs
4,590
4,450
FFs
2,670
2,620
The maximum operating frequency of the MOST NIC core depends on the selected target device,
where all supported device families operate at a minimum of 75 MHz in the lowest speed grades. Note
that the User Constraints File (UCF) provided with the core is set to a default value equivalent to the
MOST_PLL_CLK and will not match the maximum performance numbers defined. However, the user
can adjust the constraints through the UCF, as described in the MOST NIC User Guide.
Verification
Verification of the MOST NIC core has been conducted using both simulation and hardware testing to
ensure compatibility with industry-standard MOST controllers:
• Simulation. The MOST NIC has been extensively verified in functional simulations utilizing
advanced industry-standard verification techniques.
• Hardware Validation. The MOST NIC core and an example design have been tested in hardware.
Hardware validation includes interoperability testing with other MOST compatible controllers.
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DS543 September 19, 2008